Modeling of Single Spin Logic Based Hazard Free Network

Modern CMOS based advanced digital circuits suffer unwanted switching transients referred as ‘hazard’, due to ununilateral propagation delays. The hazard in combinational circuit results from a single variable change when the output should not have been altered or manipulated. The hazardous behavior of the logic circuit often creates a glitch. The glitching effect is negligible in very small circuits but when an extreme sophisticated circuits are made the glitching effect increases manifold. To address such complicated issues a new device principle of operation has come up, namely Single Spin Logic. This particular document shows how a Single Spin Logic based hazard free network is designed with adequate efficiency.